Phase locked loops (PLLs) are widely used in electronic designs such as radios, television receivers, video apparatuses, satellite broadcasts and instrumentation systems. PLLs are electronic circuits with a voltage (VCO) or current-controlled oscillator (CCO) that is constantly driven to match the frequency of an input signal. For low phase noise performance, Inductor-Capacitor (LC) type of Voltage Controlled Oscillator (LCVCO or LC-tank VCO) is used. Intrinsically, the LC-type VCOs have a small frequency tuning range. To combat process variations and to cover a wide range of frequency operations, a series of capacitor banks are needed to increase the tuning range as well as the frequency coverage range. However, parasitic capacitances from interconnect wires for connecting capacitor banks degrade the tuning range and the total frequency coverage range and need to be minimized. Minimizing the interconnect capacitance, however, results in increasing the parasitic resistances that will increase the loss of the LC-tank VCO. Therefore, LCVCO designers will need to choose an optimal interconnect wire width to make sure that the LCVCO has an enough frequency coverage range and tuning range and at the same time does not have an excessive loss that causes the LCVCO failing to oscillate. Once the parasitic capacitance is designed in, designers can only budget a certain amount of design guardband based on the worst-case interconnect resistance variations spec from the spice model. If the actual silicon interconnect resistance shifts much more than the worst-case variation spec, the LCVCO will not be able to oscillate. Similarly, the LCVCO active devices, normally a pair of cross-coupled N-channel Metal Oxide Semiconductor (NMOS) devices or a pair of cross-coupled P-channel Metal Oxide Semiconductor (PMOS) devices, have parasitic capacitances that reduce the LCVCO frequency coverage and tuning ranges and need to be reduced. The gain of the active devices is controlled to compensate the loss of the LCVCO from the parasitic resistances. Therefore, one has to make the active devices large enough to have a sufficient gain but on the other hand has to make the active devices small enough to minimize their parasitic capacitances. Again, an optimal point (active devices sizes) needs to be chosen. If the gain of the active devices in the actual silicon is much smaller than the worst-case Spice model spec, the LCVCO will not be able to oscillate.